Vertical outgassing channels

ABSTRACT

InP epitaxial material is directly bonded onto a Silicon-On-Insulator (SOI) wafer having Vertical Outgassing Channels (VOCs) between the bonding surface and the insulator (buried oxide, or BOX) layer. H 2 O and other molecules near the bonding surface migrate to the closest VOC and are quenched in the buried oxide (BOX) layer quickly by combining with bridging oxygen ions and forming pairs of stable nonbridging hydroxyl groups (Si—OH). Various sizes and spacings of channels are envisioned for various devices.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit under 35 U.S.C. §119(e) of U.S.Application Ser. No. 61/020,920, filed on Jan. 14, 2008, by Di Liang,entitled “VERTICAL OUTGASSING CHANNELS,” which application isincorporated by reference herein.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

This invention was made with Government support under Grant No.W911NF-06-1-0496 awarded by the U.S. Army. The Government has certainrights in this invention.

BACKGROUND OF THE INVENTION Description of the Related Art

(Note: This application references a number of different publications asindicated throughout the specification by one or more reference numberswithin brackets, e.g., [Ref(s). x] or in superscript form. A list ofthese different publications ordered according to these referencenumbers can be found below in the section entitled “References.” Each ofthese publications is incorporated by reference herein.)

Low-temperature direct wafer bonding is favored for dissimilar materialsintegration, particularly in III-V compound semiconductors-to-siliconintegration for attraction from desirable functionalities ofdirect-bandgap materials and standard low-cost CMOS manufacturingtechnologies.

BRIEF DESCRIPTION OF THE DRAWINGS

Referring now to the drawings in which like reference numbers representcorresponding parts throughout:

FIG. 1 illustrates the schematic of VOCs through the top non-amorphousmaterial layer to lead gas byproducts diffusing into the underneathamorphous layer for efficient outgassing.

FIG. 2 illustrates the mask design for vertical channel spacing (i.e.,density) study.

FIG. 3 illustrates a Nomaski mode microscopic image of a directly bonded2 μm thick InP epitaxial layer attached on the SOI substrate afterselectively removing the InP substrate, showing void-free bonding athighlighted area where vertical outgassing channels with 100 μm spacinglocate, while a great number of Interface voids (average density of9×10³ cm⁻², up to 1×10⁶ cm⁻², diameter 2-20 μm) appear at boundary whereno outgassing channels exist.

FIG. 4 illustrates a SEM cross-sectional image of a 6 μm wide verticaloutgassing channel with InP epitaxial material directly bonded on thetop after 2 hour anneal at 300° C.

FIG. 5 illustrates an interfacial void density vs. channel spacing andchannel area percentage for InP epitaxial layer directly bonded on SOIwith variable outgassing channel spacing. The inset shows a photographof a directly bonded 2×2 cm² InP epitaxial material on SOI with verticaloutgassing channel design, showing mirror-like, void-free epitaxiallayer transfer.

FIG. 6 illustrates an interfacial void density vs. anneal time, showingthat short anneal is achievable while low void density is stillmaintained.

FIG. 7 illustrates Nomaski-mode microscopic images of InP thin epitaxiallayers transferred to SOI substrate after 300° C. anneal (a) for 2 hourswith no outgassing channel; (b) for 15 hours with no outgassing channel;(c) for 15 hours with only in-plane outgassing channels (IPOCs)highlighted by yellow dash lines; and (d) for 15 hours with in-planeoutgassing channels and also close-loop device pattern on the SOIsubstrate. Scale bars in all figures are 200 μm.

FIG. 8 illustrates schematic cartoons of vertical outgassing channels(VOCs) on the SOI substrate (a) before and (b) after contacting with InPepitaxial layers; (c) Side-view of SEM image showing etched VOCs; (d)SEM cross sectional-view of VOCs with InP epitaxial layers bonded on thetop, showing intimate contact with no deformation or delamination.

FIG. 9 illustrates VOC pattern design of experiment to study outgassingefficiency as a function of channel spacing S and size t.

FIG. 10 illustrates Nomaski-mode microscopic images of a InP-SOI bondedpair after 300° C. anneal for 30 minutes, showing noticeable contrastbetween (a) VOC region (S=50 μm) and non-VOC corner, and (b) VOC regions(S=50 μm and 100 μm) with a 1 mm wide non-VOC margin in between.

FIG. 11 illustrates interfacial void density vs. VOC spacing of S=400,200, 100 and 50 μm, and size of t=9, 7, 5 and 3 μm for bonded pairsannealed for 2 hours at 300° C. with 3 MPa external pressure. Voiddensity on the sample in FIG. 7( a) is plotted as a reference.

FIG. 12 illustrates interfacial void density as a function of annealtime periods of 10, 20 and 120 minutes for VOC spacing of S=400, 200,100 and 50 μm, and fixed size of t=9 μm for bonded pairs annealed at300° C. with 3 MPa external pressure.

FIG. 13 illustrates interfacial void density as a function of externalpressure for bonded pairs of t=7 μm and S=100 μm after 1 hour anneal at300° C., showing that 3 MPa is required for VOC design in contrast toconventional 1.24 MPa pressure used for IPOC design. Inset: a 2×2 cm2mirror-like InP epitaxial layers transferred to the SOI substrate with 3MPa pressure applied.

FIG. 14 illustrates infrared transmission images of (a) S=50 μm and t=9μm bonded pair and (c) S=100 μm and t=7 μm bonded pair after 300° C.anneal for 30 minutes with VOC region highlighted by yellow dot-linebox. (b) and (d) are top-view microscopic images of (a) and (c),respectively, further demonstrate the strong bond at VOC regions. (e)Top-view microscopic image of a diced bonded sample with only 2 μm thickInP epitaxial layers bonded on the SOI substrate. Maximum of 6.2 μmchipping indicates high surface energy at the bonding interface.

FIG. 15 illustrates Nomaski-mode microscopic images of a InP-SOI bondedpair using another InP epitaxial wafer with relatively poorerbondability than that in FIG. (3). After 300° C. anneal for 30 minutes,similar contrast in term of void formation is visible at VOC and non-VOCregions.

FIG. 16 illustrates Nomaski-mode microscopic top-view image (a) of InPepitaxial layer transferred to the SOI substrate where some VOCs are notetched through Si device layer, shown in the SEM cross-sectional image(b) cleaved through the yellow-dash line box in (a).

FIG. 17 illustrates 50 mm (2 inch), 75 mm (3 inch) and 100 mm (4inch)InP epitaxial layers directly bonded to the SOI substrate with VOCof t=7 μm and S=100 μm after 300° C. anneal for 2-3 hours, showingmirror-like epitaxial transfer which leads to some reflection, i.e., abright bar for 50 mm one and dark bars for 75 and 100 mm ones.

FIG. 18 illustrates a process chart in accordance with one or moreembodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following description of the preferred embodiment, reference ismade to the accompanying drawings which form a part hereof, and in whichis shown by way of illustration a specific embodiment in which theinvention may be practiced. It is to be understood that otherembodiments may be utilized and structural changes may be made withoutdeparting from the scope of the present invention.

Overview

Low-temperature direct wafer bonding is favored for dissimilar materialsintegration, particularly in III-V compound semiconductors-to-siliconintegration for attraction from desirable functionalities ofdirect-bandgap materials and standard low-cost CMOS manufacturingtechnologies. Unlike mature silicon-to-silicon or SiO₂ bondingtechniques, however, low-temperature anneal (<400° C.) in compoundsemiconductor-to-silicon bonding is rigorously required to minimizethermal expansion mismatch-induced stress and potential thermal materialdegradation. Interfacial voids are likely to form at the bondinginterface due to lack of high anneal temperature to drive gas byproducts(H₂O vapor mostly and some H₂, N₂ and CO₂) out of the bonding interfaceeffectively.

The present invention demonstrates an efficient approach to achievevoid-free, low-temperature direct wafer bonding on the non-amorphousmaterial-on-amorphous material substrate, e.g., silicon-on-insulator(SOI), by employing a vertical outgassing channel (VOC) design.

Vertical Outgassing Channels

FIG. 1 shows the schematic of VOCs which are essentially holes throughthe top non-amorphous material layer to lead gas byproducts diffusinginto the underneath amorphous layer for efficient outgassing.

Although shown as InP on SOI, other materials, both amorphous andnon-amorphous, can be used within the scope of the present invention. Asshown in FIG. 1, InP epitaxial material is directly bonded onto the SOIwafer, and H₂O molecules migrating to the closest VOC are quenched inthe buried oxide (BOX) layer quickly by combining with bridging oxygenions and forming pairs of stable nonbridging hydroxyl groups (Si—OH). Inorder to study the effectiveness of this approach, VOC (6×6 μm indimension) regions with variable channel spacing of 50, 100, 200, and400 μm in FIG. 2 are patterned on 1.1×1.1 cm² SOI samples with 1 mm wideVOC-free surrounding boundaries to eliminate potential interaction fromthe adjacent sections and edges. O₂ plasma-assisted wafer bondingprocess after sample cleaning is then performed to enable InP-SOIspontaneous attachment at room temperature.

Following a short anneal (10-120 min.) at 300° C. with 1.5 MPa externalpressure, InP substrate is selectively removed in HCl solution,resulting in a ˜2 μm thick epitaxial layer transfer onto SOI. Amicroscopic image (50×) in Nomaski mode in FIG. 3 shows a drasticcontrast on a 2 hour anneal sample, where bubble-free bonding isachieved at area with VOCs (100 μm spacing) while high-density (average9×10⁴ cm²) voids distribute in boundary area uniformly, exhibiting ahighly efficient outgassing capability. In VOC region InP epitaxiallayer is tightly bonded to SOI as shown in a scanning electronmicroscopic cross-sectional image (FIG. 4) of a cleaved sample, where noInP deformation is observed in VOC area. Compared with VOC-free,directly bonded sample, interfacial void density has been reducedenormously from a conservative count of 9236 cm⁻² down to zero in FIG. 5with little different in term of channel spacing. A small real-statefootprint of <1.5% of the total bonding area is also noticed, indicatingnegligible impact to bonding strength and great freedom in device layoutdesign. The inset photograph of a 2×2 cm² InP epitaxial layer bonded onSOI exhibits the same void-free bonding, revealing a promisingperspective in bonding scalability since SiO₂ accommodation capacity perunit volume to H₂O byproduct is identical regardless of the size ofwafers. Another merit of VOC design is to enable dramatic reduction inanneal time (FIG. 6) owing to the fast gas molecules diffusion atbonding interface to VOCs. Conventional anneal time of 12-18 hoursrequired to bond the same 1 cm² InP sample onto SOI in our lab has beenreduced to 30 min while void-free bonding is still attainable in VOCregion with 50 μm spacing. Further anneal time reduction is limited bygas molecules migration to VOCs, which can be accomplished by decreasingthe channel spacing. It is finally noted that VOC approach is as wellapplicable in a variety of other bonding situations where gas byproductsneed to be removed before strong bond is initiated.

Discussion

Discussed herein are embodiments of a highly efficient scheme forlow-temperature, void-free InP-to-Silicon direct wafer bonding on a SOIsubstrate. By etching an array of small through-holes in the top siliconlayer, generated gas byproducts (H₂O, H₂) from bonding polymerizationreactions and gaseous hydrocarbon can be absorbed and diffuse in theburied oxide layer, resulting in up to 5 orders of magnitude interfacialvoid density reduction (from >50,000 cm⁻² to ≦3 cm⁻²). The requiredanneal time is reduced to less than 30 minutes, a ˜100× improvementcompared to the previous outgassing design as well. Comprehensivestudies in associated processing details, bonding surface energy,universality and stability are presented. Successful 50, 75 and 100 mmInP epitaxial layer transfer to the SOI substrate is demonstrated, whichindicates total elimination of outgassing issue regardless of the waferbonding dimension. Several incidental advantages leading to flexibledevice design, low fabrication cost, and potential bonding strain reliefare also discussed.

Introduction

Semiconductor wafer bonding has represented as an attractive, viable,large-scale hybrid material integration approach recently with thedevelopment of semiconductor wafer manufacture technology. When twomirror-polished, flat, clean wafers are brought into contact together inroom temperature, regardless of wafer material and size, Van der Waalsforce or hydrogen bond holds two wafers in position to allow bonded pairtransferred to the following stage, for example, thermal anneal forfusion bonding,¹ electric field accession for anodic bonding² or longtime storage for room temperature bonding³, all for enhancing bondingsurface energy. Since polymerization reactions are usually involved inthe surface bond formation for fusion bonding and anodic bonding,against the adhesive bonding using interfacial adhesive polymermaterials, removing the gas byproducts can be helpful to achieve strongcovalent bonds. Eqs. (1)-(2), and (3) represent the fundamentalpolymerization reactions in Si-based hydrophilic and hydrophobic directbonding⁴, respectively, all generating gas byproducts (H₂ and H₂O) whichhave been proved to be the major trapped gases at bonding interfaceexperimentally.⁵ The significant amount of gas formation and desorptionof 2-3 monolayers of water molecules at the bonding interface ofhydrophilic wafers after room-temperature mating, plus gaseoushydrocarbon from organic surface contamination during anneal, can leadto high internal pressure,⁶ subsequently resulting in local debonding,i.e., interface void formation. Typically, gas molecules with small atomsize, such as H₂, can diffuse out through the micoroughness at theinterface gradually or enter porous medium (such as SiO₂) quickly,especially at high temperatures. Interfacial voids can also be filled updue to native or thermal oxide viscous flow at high temperatures (>800°C.).⁷ Elevated temperature anneal is therefore preferred naturally dueto resulted void-free, strong bonding and its processing simplicity withno need of prebond surface activation, for example, manufacturing ofcommercial wafer-bonded silicon-on-insulator (SOI) wafers up to 300 mmin diameters.Si—OH+Si—OH→Si—O—Si+HOH  (1)Si+2H₂O→SiO₂+2H₂(g)  (2)Si—H+Si—H→Si—Si+H₂(g)  (3)

However, high temperature anneal is normally forbidden in most ofcompound semiconductors-to-silicon bonding due to thermal expansionmismatch and potential thermal material degradation or decomposition ofcompound semiconductors. Similar to Eq. (1), hydroxides of some metals Mwith high electronegativity.⁹ are also able to polymerize to formcovalent bonds at low temperatures as shown in Eq. (4). Bonding-relatedresidual gases are, therefore, inherent to the bonding mechanisms ingeneral. Embedding a thick layer of porous material such as thermal SiO₂or plasma-enhanced chemical vapor deposition (PECVD) dielectrics hasbeen reported as an efficient outgassing medium for H₂O and H₂ diffusionand absorption,^(10,11) but it is not applicable for situations wheretrue integration with proximity of two mating materials is needed.Different prebond surface treatment methods have also been employed toobtain strong InP-to-Si bonding by partially replacing surface hydroxyl(—OH) groups to other terminating groups^(12,13) though the question ofhow to effectively remove gas byproducts still remains.Si—OH+M-OH→Si—O-M+HOH  (4)

Recently a hybrid Si evanescent device platform has been developed toallow active optoelectronic components to be fabricated on the SOIsubstrate by low-temperature, O₂-plasma assisted InP-to-Si waferbonding,^(14,15) representing a breakthrough towards realization oflow-cost Si-based all optical communications. Achieving a strong,void-free bonding is of direct impact to device yield, performance andreliability. Since light travels in a type of hybrid waveguide (in a fewmicrometer dimension) composed of both thin Si device layer in the SOIsubstrate and thin InP-based compound semiconductor epitaxiallayers,^(15,16) even small local delamination in micrometer regime maycause optical scattering or loss of the hybrid waveguide structure.Top-view Nomaski-mode microscopic images (50×) in FIGS. 1( a) and (b)show the transfer of ˜2 μm thick InP epitaxial layers onto the SOIsubstrate after anneal at 300° C. for 2 hours and 15 hours,respectively. Evenly distributed interfacial voids of 2˜20 μm indiameters with a density of ˜55,093 cm⁻² indicate serious outgassingissue in FIG. 7( a). Extended anneal from 2 hours to 15 hours in FIG. 7(b) reduces the void density to ˜27,546 cm⁻², while the outgassing issueis not suppressed because bigger size voids appear due to gasaggregation from adjacent voids.

An empirical way to help outgassing is to create suitable “drainage”pipelines by etching ˜10 μm wide trenches or grooves (called “in-planeoutgassing channels (IPOCs)” in this work) on single or both wafers andextend them to the chip edges so that vacuum in postbond anneal helpspulling gas molecules out of bonding interface through IPOCs. FIG. 7( c)shows the top-view Nomaski-mode microscopic image of the InP epitaxiallayers transferred to the SOI substrate with highlighted IPOCs on theSOI substrate. The bonded pair is annealed at 300° C. in a 5×10⁻⁴ Torrvacuum for 15 hours. In contrast to FIGS. 7( a) and (b) with no any sortof outgassing channels, the area right above IPOCs in FIG. 7( c)exhibits no void formation while some of them appear in 500 μm-widechannel-free central area, indicating that the effectiveness of IPOCsdepends on the spacing of channels. However, some close-loop layout onthe SOI results in the impossibility of gas byproducts inside the loopdiffusing out through IPOCs, causing voids at channel joints as shown inFIG. 7( d) of a Si hybrid evanescent racetrack-ring resonator forexample. In addition to the disadvantage of inflexibility in SOI layoutdesign, IPOCs also become hidden trouble that undesirable gas and liquidcan diffuse back in during postbonding device fabrication and operation,which is likely to cause local debonding and device reliability issue.

Embodiments of the present invention demonstrates the design of a typeof highly efficient vertical outgassing channels (VOCs) for achievinglow-temperature, robust, void-free thin InP epitaxial layer-to-SOIdirect bonding. The VOCs concept is first presented, followed by thediscussion of fabrication process. The outgassing effectiveness of VOCs,which is evaluated by comparing interface void density on transferredthin InP epitaxial layers, is studied by varying VOCs' spacing S (i.e.density) and dimension t. Over 5 orders of magnitude void densityreduction to essentially void-free bonding interface is demonstratedwhen an optimal VOC scheme is employed. Up to 100× anneal time reductionis also showed to be sufficient for desirable bonding quality andsurface energy, highly improving the production efficiency. Theuniversality and robustness of this bonding process with VOCs ismanifested on successful transfer of III-V material with relatively poorbondability to the SOI substrate. Successful direct bonding of 50, 75 mmand 100 mm diameter InP epitaxial layers onto the SOI substrate isdemonstrated in the end to show the scalability of the bonding process.

Outgassing Principle of VOCS

As illustrated in the cartoon image of FIG. 8( a), in an embodiment VOCsare essentially an array of holes with few micrometers in size andetched through the top Si device layer to the underneath buried oxide(BOX) layer prior to contact with III-V material. Generated gasbyproduct molecules plus small amount of trapped air molecules and evengaseous impurity can migrate to the closest VOC and can promptly beabsorbed by BOX in FIG. 7( b), and gradually diffuse out through BOXlayer due to its open network with only 43% of occupied lattice space¹⁷and large diffusion cross-section (0.3-3 μm thick in general). Theunderlying chemistry of outgassing mechanism is revealed in the Eqs.(5)-(7)¹⁸.H₂O+SiO₂→Si—OH+OH—Si  (5)2Si—OH+2Si→2Si—O—Si+H₂(g)  (6)Si—O+H₂→Si—OH+OH—Si  (7)It is well-known that water vapor can reside in molecular form atinterstitial sites in SiO₂ to a depth of several hundred of angstroms inroom temperature. Upon entering the oxide network, it combines withbridging oxygen ions to form pairs of stable nonbridging hydroxylgroups, a process described in Eq. (5).^(18,19) The presence of thesehydroxyl groups in the oxide also tends to render it more porous todiffusing species,¹⁸ which is beneficial to outgassing as well. LargeHydrogen permeability in thermal SiO₂ ²⁰ expedites the absorption ofgenerated H₂ in Eqs. (2) and (7). Trapped Oxygen molecules are moreinert and do not react with the oxide network, but can react with Si ordiffuse as interstitial molecules in SiO₂ with an energy barriersensitive to the local oxide ring topology.¹⁹

FIG. 8( c) is a side-view scanning electron microscope (SEM) image ofVOCs with channel dimension t=6 μm squares and S=100 μm center-to-centerspacing. SEM cross-sectional view of a corresponding VOC with ˜2 μmIII-V epitaxial layers bonded on the top is shown in FIG. 8( d),demonstrating intimate contact of III-V and Si with no III-V deformationabove VOC. The absence and undercut of BOX is due to wet etch of SiO₂hard mask in HF solution after transferring VOC pattern from the hardmask to the Si device layer, and has no negative impact to the VOCoutgassing effectiveness. The detailed process flow is discussed below.

Experiment

VOC Patterning and Wafer Bonding Process

Commercially available 150 mm (100) SOI wafers (Boron doped, 1-10Ohm-cm) used in this work contain 1 μm Si device layer and 1 μm buriedoxide (BOX) layer. Although described as performed, other thicknessesand process parameters are possible and within the scope of the presentinvention. Patterning VOCs in the SOI substrate starts from growing 1 μmSiO₂ in wet oxidation to be the hard mask after a modified RCA1(NH₄OH:H₂O₂:H₂O=0.2:1:5, 80° C.) cleaning for 10 minutes²¹ and nativeoxide removal in HF solution (0.5%) for 30 seconds. Standard contactphotolithography is conducted, followed by transferring VOC pattern toSiO₂ hard mask in buffered HF (BHF) solution (HF:H₂O=1:7) for ˜10minutes. Upon stripping off photoresist in Acetone, the pattern is thenfurther transferred to Si device layer by inductively coupled plasmareactive ion etching (ICP-RIE) silicon etch in BCl₃/Cl₂ plasma. Prior toremoving the SiO₂ hard mask, the SOI sample is cleaned again in asolution of H₂SO₄:H₂O₂=3:1 at 100° C. for 10 minutes, leaving adust-free surface. The InP-based III-V sample cleaved from the 50 mmmetal-organic chemical vapor deposition (MOCVD)-grown epitaxial wafer iscleaned in Acetone and Isopropyl Alcohol with gentle physical swab.After removing the SiO₂ hardmask on the SOI sample and native oxide onthe III-V sample in BHF and NH4OH (39%) solutions, respectively, O₂plasma surface treatment is proceeded on both samples in a commercialEVG 801 LowTemp Plasma Activation System for 30 seconds. A thin (<5 nm)layer of highly strained native oxide is grown on both SOI and III-Vsamples,²² resulting in a very reactive hydrophilic surface.Subsequently high surface hydroxyl groups (—OH) density after contactwith solution rich of hydroxyl groups, for example H₂O or H₂O-richsolutions, is attainable.⁴ So the final activation step involvesterminating the hydrophilic surfaces with hydroxyl groups. It has beenreported that surface activation in NH₄OH solution resulted in higherbonding surface energy due to the conversion of some Si—OH to Si—NH₂with higher bond strength.^(21,23) Instead of dipping the samples inNH₄OH solution directly,^(21,23) a NH₄OH vaporization process isdeveloped to result in a more uniform and cleaner surface activation²⁴The SOI and III-V samples are placed on a 125° C. hotplate with a glasscover for 5 minutes to introduce NH₄OH vapor and vaporize liquid trappedin the VOC cavities, avoiding the gasification in the following elevatedtemperature anneal which can subsequently cause debonding. Spontaneousmating at room temperature is then carried out manually. Furtherannealing at 300° C. is conducted in a commercial Suss SB6E wafer bonderto obtain strong covalent bonding. Relatively high external pressure isrequired to obtain high quality bonding, which is discussed below. TheInP substrate is finally etched off in a solution of HCl:H₂O=3:1 at roomtemperature, leaving 200 nm InGaAs etch stop layer and the rest of 2 μmthick InP-based epitaxial layers on the SOI substrate. Due to thefragility and pliability of thin InP epitaxial layers, small deformationdue to local internal pressure from outgassing or stress appearsinstantly after the substrate is removed. The interfacial void densityis then obtained by carefully counting void number under a microscope inNomaski-mode for the best contrast.

Design of Experiment (DOE)

In order to study the outgassing efficiency of VOCs, a pattern withvariable VOC spacing S and dimension t was designed. FIG. 9 shows theVOC mask of a 9×9 mm² square area for patterning 1×1 cm² SOI sample with1 mm wide stripe region around the edge for photoresist edge beadremoval. Four 3×3 mm² square regions with VOC spacing of 50, 100, 200,and 400 μm are located on the 9×9 mm² mask area with 1 mm VOC-freemargin to each other and the sample edge, minimizing the interactionamong different regions and possible gas product diffusion and escapefrom the sample edge. Square shape is used for all VOCs with thedimension varying from 2, 4, 6, to 8 μm on four respective mask areas.

Results and Discussion

Interfacial Void Density Studies

Red dash-line boxes in FIGS. 10( a) and (b) of Nomaski-mode microscopicimages (50×) highlight a VOC region of S=50 μm around the sample corner,and regions of S=50 μm (left) and S=100 μm (right) with 1 mm VOC-freemargin in between, respectively. The actual VOCs on the SOI substrateare about 9×9 μm² square holes with slightly rounded angles due toisotropic BHF wet etch in patterning the SiO₂ hard mask. The bonded pairis annealed at 300° C. for only 30 minutes with about 3 MPa externalpressure applied. Evident void density reduction down to nearly zero isvisible in VOC region of FIG. 10( a) while a great number of uniformlydistributed voids still exist at VOC-free corner with density slightlydecreasing towards VOC region due to smaller diffusion path to VOCs. Asimilar situation is exhibited in FIG. 10( b) where VOC-free centralarea with many voids is sandwiched by void-free S=50 μm and S=100 μmregions.

FIG. 11 represents the relationship of interfacial void density vs.channel spacing S with different channel dimension t for bonded pairsafter 300° C. anneal for 2 hours. Dramatic void density reduction up to5 orders of magnitude is achieved from the sample with no outgassingchannel to that of S=50 μm region. Decreasing channel spacing S, i.e.increasing channel density, greatly enhances the possibility for gasbyproducts and monolayers of surface water to migrate to VOCs andsubsequently quenched by the BOX layer, before aggregating aroundpreferable sites, such as hydrocarbon surface contamination and surfacedefects.^(5,11) Compared with bonded pairs without outgassing channel inFIGS. 7( a) and (b), the sample with S=400 μm already reduces the voiddensity by more than 36×. Bonded pair with VOC of S=100 μm isequivalently good as the one with IPOCs which is required to anneal for15-18 hours instead. For the case of S=50 μm, less than 10 cm⁻² voiddensity for voids less than 20 μm in diameter is considered to be theoutgassing issue completely eliminated since it becomes impossible todifferentiate outgassing-induced voids (i.e., “intrinsic” voids) withsurface contamination and surface defect-induced ones (i.e., “extrinsic”voids) for manually cleaning and bonding in a Class 100-1000 cleanroom.Channel spacing S, therefore, is the first-order influence factor foroutgassing. FIG. 11 shows that larger channel size t also contributes toslightly lower void density since larger channel and exposed BOX squarearea offers stronger gas byproduct accommodation capability in the unittime period. Larger t also means slightly smaller effective contactarea, i.e., less surface hydroxyl groups to contribute gas byproductgeneration. Hence, parameter t becomes the second-order influence factorfor outgassing. It is noted that void density data in FIG. 11 areaverage numbers obtained from bonding 1 cm² samples with four isolatedchannel regions (FIG. 9) and 1 cm² individual ones with single VOCscheme.

It is well-known that longer anneal time normally leads to strongerbonding surface energy which starts saturating to a maximum value aftercertain period of anneal time when generated gas byproducts are removedfrom the bonding interface completely, either by absorption ordiffusion.^(11,25) Thus, it is of interest to determine if there is asimilar outgassing efficiency threshold in term of anneal time.Interfacial void density as a function of anneal time at 300° C. isrevealed in FIG. 12. Similar outgassing efficiency is found on bondedpairs annealed for 2 hours and 30 minutes while the one with only 10minute anneal shows significantly higher void density, indicating thatoutgassing efficiency firstly relies on the gas transportation to theVOCs, a function of time periods. The minimum anneal time at 300° C.anneal temperature in this work is likely to be around 30 minutes forthe best outgassing efficiency. Further anneal time reduction in thistemperature is believed to be attainable by reducing VOC spacing S. Wenote here that previous low-temperature bonding with IPOCs needs15˜18-hour anneal to obtain low void density (10-20 cm⁻²) bonding,comparable to that of 30-minute anneal with VOC design. Zhang et al.studied the void formation in low-temperature Si—Si bonding without anytype of outgassing channels.¹¹ Quite long anneal time (>100 hours insome cases) was founded necessary to reach saturation of bondingpolymerization reactions, and stop new void formation,¹¹ which supportsthe argument here that the efficiency in gas byproducts removaldetermines the bonding quality and required anneal time, i.e. productionefficiency.

Unlike the bonding process with IPOCs, however, embodiments of the newprocess with VOC design uses higher external pressure to hold samples inposition and prevent the debonding or local deformation of III-Vmaterial since trapped air in VOCs expands as soon as temperatureramping begins. Assuming a potentially worst case that the mass oftrapped cleanroom ambient air (99% of O₂ and N₂) is constant (i.e., noabsorption or diffusion in Si or BOX layer) through the entiretemperature cycling from room temperature (20° C.) to 300° C. and backto room temperature, the additional pressure can be calculated from thewell-known Gay-Lussac's Law in Eq. 8 since O₂ and N₂ can be treated asan ideal gas at relatively low temperature. T. P_(T) and P₀ in Eq. 8represent the temperature T in Celsius degree and the pressures attemperature T and 0, respectively. The maximum internal pressure ofP_(300° C.) in a VOC cavity is, therefore, 1.96 times of the pressure at20° C., P_(20° C.) at which VOC cavity is formed upon spontaneousmating. P_(20° C.) in this work is also equal to the pressure of 1.24MPa routinely used for bonding pairs with IPOCs in our lab in order tominimize the surface microroughness on III-V surface, because no gasexpansion takes place in vacuum anneal chamber for IPOC case. Thus, apressure of 2.43 MPa is used to overcome the gas expansion and achievethe same quality bonding for VOC case as that of IPOC case.

$\begin{matrix}{P_{T} = {P_{0}\left( {1 + {\frac{1}{273.15}T}} \right)}} & (8)\end{matrix}$

FIG. 13 shows the experimental data of interfacial void density vs.external pressure for bonded pairs with t=7 μm and S=100 μm after 300°C. anneal for 1 hour. Extremely high average void density over 4000 cm⁻²appears at bonded pair with no external pressure applied as expected,and decreases to around 290 cm⁻² when the regular 1.24 MPa used for IPOCcase is applied. Low void density of 27 cm⁻², comparable to IPOC case(18 hour anneal), is obtained when pressure is increased to 3 MPa, 2.41×of 1.24 MPa. The slightly higher pressure in experiments thancalculation from Gay-Lussac's model is believed due to the contributionof aggregation of H₂O gas byproduct and small amount of trapped, tinyairborne organic particles, plus the potential error of the idealGay-Lussac's model for the actual situation. Inset image in FIG. 13 is a2×2 cm² sample annealed for 2 hours at 300° C. with 3 MPa externalpressure. A mirror-like epitaxial layer transfer is achieved afterselectively removing the InP substrate. Lower pressure would besufficient if spontaneous mating at room temperature is conducted in avacuum environment.

Bonding Strength Characterization

It is not practical to apply external pressure during postbonding deviceprocessing (up to 320° C.) after removing the InP substrate. Preventionof III-V delamination due to trapped gas expansion in VOC cavitiesrelies on the surface energy of bonded area around VOCs. Hence, bondingstrength (i.e., surface energy) after anneal stands as another factor inevaluating the bonding quality. In a Class 1000 cleanroom environmentthe standard crack-opening method²⁶ is performed on about 1×1 cm² bondedpairs which are annealed for only 30 minutes since it appears to besufficient for efficient outgassing in FIG. 12. Longer anneal timenormally results in equal or higher surface energy²⁵ so that only30-minute annealed samples are used for this measurement. Two oppositeedges of SOI samples used in this measurement are angularly polished toa 45° angle to the bonding surface, allowing a 100 μm thin bladeinserted into the bonding interface easily, correctly, and repeatably.The top InP samples with ˜400 μm InP substrate remaining, however, areall broken at or before reaching the boundary of contacted areaconsistently as shown in void-free infrared transmission images of FIGS.14( a)-(d), when the blade is attempted to insert through, resulting infailure to determine the equilibrium crack length. Yellow dot-line inFIGS. 14( a) and (c) highlights the contacted areas with respective VOCsof S=50 μm and t=9 μm, and S=200 μm and t=7 μm, showing the crack of InPsubstrate close the edge of the VOC pattern. Blade stops at thepositions shown in the figures when crack of InP presents. FIGS. 14( b)and (c), the respective top-view microscopic (25×) images for the bluedash-line boxes in FIGS. 14( a) and (c), further confirm the maintainingof intimate InP-SOI contact so that InP breakage follows the contactboundary strictly. A small fringe of the top Si layer, between exposedBOX green border (from the step of photoresist edge bead removal) andInP substrate in FIG. 14( d), indicates relatively lower surface energycompared to the bonded pair with S=50 μm and t=9 μm in FIG. 14( b),which is expected due to significantly higher void density shown in FIG.11. The crack of the InP substrate on small size samples indicates thelikelihood of the bonding surface energy higher than the fracture energyof bulk InP,²⁴ a similar case that Maszara reported in measuringhydrophilic Si—Si bond as well.¹ Accurate determination of the bondingsurface energy requires a thinner blade and larger size samples withthicker InP substrate, which is much more expensive and beyond the scopeof this work.

Alternatively, III-V-SOI bonded samples experience a harsh dicing test,a standard process for fabricating the Febry-Perot cavity devices aswell. The bonded sample with only 2.2 μm thick epitaxial layers on theSOI substrate is cut by a 100 μm thick blade with over 10,000 rounds/minspin rate. Though the III-V side is up and there is no surfaceprotection during dicing, the chipping of III-V epitaxial layer is nomore than 6.2 μm and follows the SOI fringe consistently in FIG. 14( e),also demonstrating the achievement of strong bonding. The III-Vepitaxial material is covered by a layer of dicing dust shown in FIG.14( e), proving no any sort of surface protection is employed during thedicing test.

Another thermal cycling step of baking bonded pairs to 250° C. in theair for 5-10 minutes after the InP substrate removal is routinelypursued to further verify the bonding strength since any voids withtrapped gas byproducts at bonding interface become more visible then. Onthe other hand, remaining gases in VOC cavities would be able to causedelamination in this bake step if the bonding strength was notsufficiently strong to hold the III-V epitaxial layer and SOI together.No noticeable deformation or delamination of transferred III-V layers ator around VOCs is found, indicating high surface energy in the entirecontacted area and possible decrease of gas pressure inside VOC cavitiesby either absorption or diffusion. Void densities of S=50 μm and 100 μmcases remain the same after an additional bake (data not shown), showingthe completed outgassing process and excellent reliability of thebonding process. The same test is performed on the sample bonded over 2months earlier, and no change in term of void density and III-Vdeformation is noticed (data not shown), which indicates that H₂Oabsorption in the BOX layer (Eq. (5)) is not reversible as well.

It is also interesting to note here that interfacial void formationcharacteristic is closely associated with surface states of materials,including surface roughness, surface epitaxial defects and hydroxylgroup density after O₂ plasma treatment, etc. FIGS. 15( a) and (b)reveal the similar areas of bonded pair with III-V material from adifferent vendor after 300° C. anneal for 30 minutes as shown in FIG.10. Unlike the high density of small size voids (<20 μm in diameter) inFIG. 10( a), voids in non-VOC areas display arbitrary shapes with evenmore than 200 μm in one direction in FIG. 15, primarily due to a largernumber of surface defects in this epitaxial wafer which are preferablenucleation sites for gas aggregation¹¹ and slightly rougher surfacewhich is helpful for gas byproduct migrating relatively long distance togather at nucleation sites. Bonding on 1 cm² sample without VOCs orIPOCs fails (data not shown) because the InP epitaxial layers aretotally peeled off during post-anneal substrate removal in HCl solution,indicating a intrinsically poorer bondability of this type of wafer andserious outgassing problem. Nevertheless, high-quality, void-freebonding is still attainable with the help of VOCs as shown in FIG. 15where regions of S=100 μm and 50 μm (t=9 μm) are highlighted with redboxes. It demonstrates the robustness and universality of this processwhich can potentially lowers the criteria for bonding wafer selection,greatly reducing the overall manufacture cost. It should also be notedthat although the VOC model discussed above describes the generaloutgassing principle with the help of a “gutter” layer, such as the BOXlayer in this work, the values of interfacial void density observed inour experiments represent only those particular sets of wafers tested inparticular conditions. More detailed studies on interfacial voidformation characteristic associated with SOI and III-V materialproperties, surface chemistry and bonding process is under way.

Finally the outgassing mechanism proposed and demonstrated in this paperis further confirmed by accidentally not etching down to the BOX layeras shown in FIG. 16( b), a SEM cross-sectional image of a yellowdash-line highlighted region in FIG. 16( a). Due to the photoresistbuild-up at the edge of the sample, some VOC pattern is not transferredto the SiO₂ hardmask perfectly, resulting in Si device is not completelyetched through in some VOCs. Aggregated gas and trapped gas in VOCscause the noticeable deformation of InP thin epitaxial layers, shown bythose bouffant bubbles in some VOCs sites in FIG. 16( a). Cleavingthrough the bubble in FIG. 16( b) releases trapped gases andsubsequently the internal pressure, but poor bonding surface energy canbe qualitatively judged by perfect InP breakage along its (100)crystalline orientation. Unlike the strong bonding showed in a similarcross-sectional view in FIG. 8( d), poor bonding in FIG. 16( b) resultsin the Si and InP broken independently upon cleave, showing nice (100)facet on InP and rough facet on Si device layer.

Bonding Scalability

According to the FIGS. 11-13, each VOC appears capable of accommodatinglimited gas byproducts from neighboring region in a certain time period,resulting in an effective area coverage as a VOC at the center. Ideal,void-free bonding can be achieved as long as area coverage startsoverlapping each other, eliminating the existence of the “dead zone”,which is most likely to be the case of S=50 μm in this work. In anotherword, outgassing issue can be fundamentally eliminated if VOCs withappropriate scheme is employed, regardless of the wafer dimension. FIG.17 demonstrates the successful transfer of 50 mm (2 inch), 75 mm (3inch) and 100 mm (4 inch) in diameter InP-based epitaxial layer onto theSOI substrate with VOCs of S=100 μm and t=7 μm. The bonded wafers areannealed at 300° C. for 2-3 hours with 3 MPa pressure, showing the samebonding quality as 1 cm² samples. To our best knowledge, 4 inch bondinghere is the record large InP-to-Si direct wafer bonding, i.e. nointerfacial oxide or polymer adhesion layer. The success to applying thesame bonding process to variable size of wafer bonding demonstratespromising process scalability with VOCs provided that wafers are clean,flat and smooth.

Additional Advantages

It is finally noted that the design of some embodiments of VOCs canembrace several more merits and processing convenience in addition tothose discussed before.

In contrast to previously used IPOCs where gas and liquid can flow backin, bonding with VOCs isolates the bonding interface from the outsideenvironment substantially completely in some embodiments, improving thebonding stability. Furthermore, the negative impact of local III-Vbreakage or peel-off due to interface particles, surface scratches ordefects is small (data not shown) since the rest of bonded area is notsubject to damage by hazardous gas or liquid.

A flexible device pattern design is available owing to the compatibilityof the vertical outgassing process with conventional in-plane circuitsand component layout.

Small footprint on SOI substrate even for VOCs with small spacing andrelatively large dimension (i.e., S=50 μm and t=9 μm in this work) isresulted in some embodiments. Table 1 lists the percentage of unbondedarea due to the absence of etched Si material. The maximum of 3.24% areaconsumption leaves plenty of room for high-density device integration,and optical, electrical and thermal interaction between SOI and III-Vlayers.

Preliminary X-ray diffraction study (data not shown) indicates that VOCsmay even serve as “stress-relieving” pattern,²⁷ contributive to voidsuppression, allowing the thermally mismatched films to withstandpostbonding device processing, and minimizing stress-induced defects.Further investigation is required to understand the underlying physics.

There are multiple ways to pattern and form VOCs which can be in variousshapes of square, circle, rectangle, etc. or their combinations. Thethermal anneal with VOCs doesn't require vacuum or forming gas either.No difference is noticeable for using SOI wafers with 1 μm and 3 μm BOXlayer. They all result in desirable fabrication flexibility and low-costprocess.

Process Chart

FIG. 18 illustrates a process chart in accordance with one or moreembodiments of the present invention.

Box 1800 illustrates patterning the first wafer with an array ofchannels, wherein the channels connect a bonding surface of the firstwafer with a buried oxide layer of the first wafer.

Box 1802 illustrates coupling the bonding surface of the first waferwith a top surface of the second wafer.

Box 1804 illustrates heating the coupled first wafer and second wafer.

Box 1806 illustrates and cooling the coupled first wafer and secondwafer to mate the first wafer to the second wafer.

CONCLUSION

A simple, novel vertical outgassing channel (VOC) concept is introducedand the underlying chemistry is discussed in detail. The primary gasbyproducts of H₂O and H₂ from bonding polymerization reactions at lowtemperature are absorbed by the thick BOX layer in SOI substrate throughVOCs. Dramatic interfacial void density reduction up to five orders ofmagnitude (from >50000 cm⁻² to ≦3 cm⁻²) is demonstrated on properlyselected VOC scheme when only thin InP epitaxial layers are left on theSOI substrate, showing extremely efficient outgassing capability. Therequired minimum anneal time period at 300° C. is between 10-30 minutesfor optimal bonding quality, a time period for the entire outgassingprocess to complete as well. It represents 36-108× time reductioncompared to the previous in-plane outgassing channel (IPOC) design, andis an even larger reduction for the case of no outgassing channel. 3 MPaexternal pressure is experimentally found necessary to overcome theexpansion of trapped air in VOC cavities. Bonding strength ischaracterized by crack-opening method and a harsh dicing test, bothshowing high surface energy. An additional thermal bake step alsoexhibits the stability and reliability of bonding with VOCs. Therobustness and universality of this VOC design is confirmed by the samedemonstrated outgassing efficiency when the identical process is appliedto two different InP epitaxial wafers with good and poor bondability. Asuccessful epitaxial transfer of a 75 mm InP wafer to SOI substrateunfolds the promising perspective to further scale it up to larger sizefor mass production, indicating that VOC design is waferscale-independent and representing an approach to fundamentally resolvethe outgassing issue in semiconductor-on-insulator-based direct waferbonding. Several incidental advantages in device design and fabrication,bonding reliability, and bonding stress minimization are mentioned aswell. The same outgassing principle can thus be applied to otherlow-temperature homogeneous or dissimilar material integration with agutter layer involved. Further, other substrate materials besidessilicon and InP, such as other III-V or 1′-VI materials, germanium, orother materials, can be used as either or both substrates within thescope of the present invention.

Described herein are wafer bonded devices with channels to improve thebonding of the devices. A wafer bonded device in accordance with one ormore embodiments of the present invention comprises a substrate waferhaving a buried oxide layer and a bonding layer, the bonding layerhaving at least one outgassing channel coupled between a bonding surfaceof the bonding layer and the buried oxide layer, and a second wafer,bonded to the bonding surface of the bonding layer.

Such a device further optionally comprises the at least one outgassingchannel reducing interfacial void density between the substrate waferand the second wafer, the at least one outgassing channel being aplurality of outgassing channels, the plurality of outgassing channelsbeing arranged in an array, the plurality of outgassing channels havinga consistent cross sectional shape, the consistent cross sectional shapebeing a substantially square cross sectional shape, an edge of thesquare cross sectional shape being between 2 and 10 microns, the arrayhaving a consistent spacing, the consistent spacing being selected asbeing a distance between 50 and 400 microns, the substrate wafer being asilicon wafer, and the second wafer being a III-V wafer.

A method for bonding a first wafer and a second wafer in accordance withone or more embodiments of the present invention comprises patterningthe first wafer with an array of channels, wherein the channels connecta bonding surface of the first wafer with a buried oxide layer of thefirst wafer, coupling the bonding surface of the first wafer with a topsurface of the second wafer, heating the coupled first wafer and secondwafer, and cooling the coupled first wafer and second wafer to mate thefirst wafer to the second wafer.

Such a method further optionally comprises annealing the mated first andsecond wafers, and pressurizing the mated first and second wafers.

A heterojunction device in accordance with one or more embodiments ofthe present invention comprises a first substrate, comprising a devicelayer and a buried layer, wherein the device layer comprises at leastone channel coupled between a top surface of the device layer and theburied layer, and a second substrate comprising an active layer, whereinthe top surface of the device layer of the first substrate is waferbonded to the active layer of the second substrate.

Such a device further optionally comprises the at least one channelreducing interfacial void density between the top surface of the devicelayer and the active layer of the second substrate, the at least onechannel being a plurality of channels, the plurality of channels beingarranged in an array, the array having a consistent spacing, and theconsistent spacing being selected as being a distance between 50 and 400microns.

REFERENCES

The following references are incorporated by reference herein:

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This concludes the description of the preferred embodiment of thepresent invention. The foregoing description of one or more embodimentsof the invention has been presented for the purposes of illustration anddescription. It is not intended to be exhaustive or to limit theinvention to the precise form disclosed. Many modifications andvariations are possible in light of the above teaching. It is intendedthat the scope of the invention be limited not by this detaileddescription, but by the claims which form a part of this application,and the full range of equivalents of the claims.

What is claimed is:
 1. A wafer bonded device, comprising: a substratewafer having a buried oxide layer and a bonding layer, the bonding layerhaving at least one outgassing channel coupled between a bonding surfaceof the bonding layer and the buried oxide layer; and a second wafer,bonded to the bonding surface of the bonding layer, wherein gasbyproducts traverse the at least one outgassing channel and diffuse intothe buried oxide layer.
 2. The wafer bonded device of claim 1, whereinthe at least one outgassing channel reduces interfacial void densitybetween the substrate wafer and the second wafer.
 3. The wafer bondeddevice of claim 2, wherein the at least one outgassing channel is aplurality of outgassing channels.
 4. The wafer bonded device of claim 3,wherein the plurality of outgassing channels are arranged in an array.5. The wafer bonded device of claim 4, wherein the plurality ofoutgassing channels have a consistent cross sectional shape.
 6. Thewafer bonded device of claim 5, wherein the consistent cross sectionalshape is a substantially square cross sectional shape.
 7. The waferbonded device of claim 6, wherein an edge of the square cross sectionalshape is between 2 and 10 microns.
 8. The wafer bonded device of claim4, wherein the plurality of outgassing channels in the array have aconsistent spacing.
 9. The wafer bonded device of claim 8, wherein theconsistent spacing is selected as being a distance between 50 and 400microns.
 10. The wafer bonded device of claim 1, wherein the substratewafer is a silicon wafer.
 11. The wafer bonded device of claim 1,wherein the second wafer is a III-V wafer.